Embodiments of the invention relate generally to semiconductor device packages or electronics packages and, more particularly, to an electronics package that includes a conductor layer with locally varied thicknesses. This multi-thickness conductor layer combines high current carrying capabilities and a high density interconnection structure into a common horizontal plane, which facilitates the integration of different types of electronics devices in a miniaturized package topology.
As semiconductor device packages have become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminated-based ball grid array (BGA) packaging, to chip scale packaging (CSP), then flipchip packages, and now buried die/embedded chip build-up packaging. Advancements in semiconductor chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability.
A challenge to existing manufacturing techniques is the miniaturization of electronics packages that incorporate different types of individually packaged semiconductor dies that have different current carrying and routing density requirements, such as a mixture digital semiconductor devices and power semiconductor devices. The general structure of a prior art electronics package 10 incorporating a number of individually packaged components 12, 14, 16, 18 is shown in FIG. 1. The individually packaged components 12, 14, 16, 18 are mounted on a multi-layer printed circuit board (PCB) 20 that has a thickness 22 of approximately 31 to 93 mils. The individually packaged components 12, 14, 16, 18 may be power semiconductor packages, packaged controllers, or other discrete electrical components such as inductors or passive components that are coupled to electrical contacts 24 of PCB 20 using metalized connections 26 such as, for example, solder balls in the form of a ball grid array (BGA).
In the illustrated example, individually packaged devices 14, 16 each include a respective semiconductor device or die 28, 30 having contact pads 32 formed on an active surface thereof. Die 28, 30 are provided on a mounting platform 34, 36 and encased within an insulating material 38, 40. Wirebonds 42, 44 form direct metal connections between active surfaces of respective die 28, 30 and a metalized input/output (I/O) provided on or coupled to the lower surface of die 28, 30. In the case of discrete component 14, wirebonds 42 form an electrical connection between contact pads 32 of die 28 to I/O pads 46 provided on a bottom surface of discrete component 14. Wirebond 42 electrically couples contact pads 32 to I/O leads 48. Where die 30 is a diode, for example, wirebond 42 may connect to the anode on a first surface of the die 30 and a second surface of the die 30 may be soldered to the leadframe. I/O pads 46 and I/O leads 48 are coupled to electrical contacts 24 of PCB 20 by way of metalized connections 26. The overall thickness 50 of such prior art IC packages may be in the range of 500 μm-2000 μm or larger.
Alternatively, electrical connections between components may be realized using a combination of thick and thin conductor layers that are electrically connected to the appropriate semiconductor dies or power devices using through hole or via technology. However, inclusion of multiple routing layers adds considerable thickness to the overall electronics package, a factor that in combination with the complex conductor structure, limits product level miniaturization, design flexibility, and cost efficiency. Additionally, both of the aforementioned techniques include multiple routing layers, which results in a long and complex conductor structure between electrical components and weakens the electrical performance of the overall package, which is increasingly unfavorable in high performance packaging (e.g., high frequency, RF, intelligent power, and other advanced electronics packaging).
Accordingly, it would be desirable to provide a new electronics packaging technology that permits electrical components of different types to be integrated into a highly miniaturized electronics package with locally enhanced electrical and thermal conductivity for certain electronics components and increased routing density in regions proximate other electronics components. It would further be desirable for such a packaging technology to permit a shorter conductor length between electrical components and improve signal fidelity.